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PA-RISC

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PA-RISC (HP/PA)
DesignerHewlett-Packard
Bits64-bit (32→64)
Introduced1986 (1996 PA-RISC 2.0)
Version2.0 (1996)
DesignRISC
EncodingFixed
BranchingCompare and branch
EndiannessBig
ExtensionsMultimedia Acceleration eXtensions (MAX), MAX-2
OpenNo
SuccessorPA-WideWord → Itanium[1]
Registers
General-purpose32
Floating point32 64-bit (16 64-bit in PA-RISC 1.0)
HP PA-RISC 7300LC microprocessor
HP 9000 C110 PA-RISC workstation booting Debian GNU/Linux

Precision Architecture RISC (PA-RISC) or Hewlett Packard Precision Architecture (HP/PA or simply HPPA), is a general purpose computer instruction set architecture (ISA) developed by Hewlett-Packard from the 1980s until the 2000s.

The architecture was introduced on 26 February 1986, when the HP 3000 Series 930 and HP 9000 Model 840 computers were launched featuring the first implementation, the TS1.[2][3] HP stopped selling PA-RISC-based HP 9000 systems at the end of 2008 but supported servers running PA-RISC chips until 2013.[4] PA-RISC was succeeded by the Itanium (originally IA-64) ISA, jointly developed by HP and Intel.[5]

History

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In the late 1980s, HP was building four series of computers, all based on CISC CPUs. One line was the IBM PC compatible Intel i286-based Vectra Series, started in 1986. All others were non-Intel systems. One of them was the HP Series 300 of Motorola 68000-based workstations, another Series 200 line of technical workstations based on a custom silicon on sapphire (SOS) chip design, the SOS based 16-bit HP 3000 classic series, and finally the HP 9000 Series 500 minicomputers, based on their own (16- and 32-bit) FOCUS microprocessor.

The Precision Architecture is the result of what was known inside Hewlett-Packard as the Spectrum program.[6] HP planned to use Spectrum to move all of their non-PC compatible machines to a single RISC CPU family.

In early 1982, work on the Precision Architecture began at HP Laboratories, defining the instruction set and virtual memory system. Development of the first TTL implementation started in April 1983. With simulation of the processor having completed in 1983, a final processor design was delivered to software developers in July 1984. Systems prototyping followed, with "lab prototypes" being produced in 1985 and product prototypes in 1986.[7]

The first processors were introduced in products during 1986. It has thirty-two 32-bit integer registers and sixteen 64-bit floating-point registers. The HP Precision Architecture has a single branch delay slot. This means that the instruction immediately following a branch instruction is executed before the program's control flow is transferred to the target instruction of the branch.[8][9] An HP Precision processor also includes a Processor Status Word (PSW) register. The PSW register contains various flags that enable virtual addressing, protection, interruptions, and other status information.[10] The number of floating-point registers was doubled in the 1.1 version to 32 once it became apparent that 16 were inadequate and restricted performance. The architects included Allen Baum, Hans Jeans, Michael J. Mahon, Ruby Bei-Loh Lee, Russel Kao, Steve Muchnick, Terrence C. Miller, David Fotland, and William S. Worley.[11]

The first implementation was the TS1, a central processing unit built from discrete transistor–transistor logic (74F TTL) devices. Later implementations were multi-chip VLSI designs fabricated in NMOS processes (NS1 and NS2) and CMOS (CS1 and PCX).[12] They were first used in a new series of HP 3000 machines in the late 1980s – the 930 and 950, commonly known at the time as Spectrum systems, the name given to them in the development labs. These machines ran MPE-XL. The HP 9000 machines were soon upgraded with the PA-RISC processor as well, running the HP-UX version of UNIX.

Other operating systems ported to the PA-RISC architecture include Linux, OpenBSD, NetBSD, OSF/1, NeXTSTEP, and ChorusOS.[13]

An interesting aspect of the PA-RISC line is that most of its generations have no level 2 cache. Instead large level 1 caches are used, initially as separate chips connected by a bus, and later integrated on-chip. Only the PA-7100LC and PA-7300LC have L2 caches. Another innovation of the PA-RISC is the addition of vector instructions (SIMD) in the form of MAX, which were first introduced on the PA-7100LC.

Precision RISC Organization, an industry group led by HP, was founded in 1992, to promote the PA-RISC architecture. Members included Convex, Hitachi, Hughes Aircraft, Mitsubishi, NEC, OKI, Prime, Stratus, Yokogawa, Red Brick Software, and Allegro Consultants, Inc.

The ISA was extended in 1996 to 64 bits, with this revision named PA-RISC 2.0. PA-RISC 2.0 also added fused multiply–add instructions, which help certain floating-point intensive algorithms, and the MAX-2 SIMD extension, which provides instructions for accelerating multimedia applications. The first PA-RISC 2.0 implementation was the PA-8000, which was introduced in January 1996.

CPU specifications

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Image Model Marketing
name		 Year Frequency
[MHz]		 Memory Bus
[MB/s]		 Process
[μm]		 Transistors
[millions]		 Die size
[mm²]		 Power
[W]		 Dcache
[KB]		 Icache
[KB]		 L2 cache
[MB]		 ISA Notes
TS-1 ? 1986 8 ? ? — — ? 64 64 — 1.0 [14]
CS-1 ? 1987 8 ? 1.6 0.164 72.93 1 — 0.25 — 1.0 [15]
NS-1 ? 1987 25/30 ? 1.7 0.144 70.56 ? 16-128 16-128 — 1.0 [14][16] Unified L1 cache
NS-2 ? 1989 25/30 ? 1.5 0.183 196 27 512 512 — 1.0 [17]
PCX ? 1990 50/60 ? 1.0 0.196 ? ? ? ? ? 1.0 [14]
PCX-S PA-7000 1991 66 ? 1.0 0.58 201.6 ? 256 256 — 1.1a
PCX-T PA-7100 1992 33–100 ? 0.8 0.85 196 ? 2048 1024 — 1.1b
PCX-T PA-7150 1994 125 ? 0.8 0.85 196 ? 2048 1024 — 1.1b
PCX-T' PA-7200 1994 120 960 0.55 1.26 210 30 1024 2048 — 1.1c
PCX-L PA-7100LC 1994 60–100 ? 0.75 0.9 201.6 7–11 — 1 2 1.1d
PCX-L2 PA-7300LC 1996 132–180 ? 0.5 9.2 260.1 ? 64 64 0–8 1.1e
PCX-U PA-8000 1996 160–180 960 0.5 3.8 337.68 ? 1024 1024 — 2.0
PCX-U+ PA-8200 1997 200–240 960 0.5 3.8 337.68 ? 2048 2048 — 2.0
PCX-W PA-8500 1998 300–440 1920 0.25 140 467 ? 1024 512 — 2.0 [18]
PCX-W+ PA-8600 2000 360–550 1920 0.25 140 467 ? 1024 512 — 2.0 [18]
PCX-W2 PA-8700(+) 2001 625–875 1920 0.18 186 304 <[email protected] V 1536 768 — 2.0
Mako PA-8800 2003 800–1000 6400 0.13 300 361 ? 768/core 768/core 0 or 32 2.0
Shortfin PA-8900 2005 800–1100 6400 0.13 ? ? ? 768/core 768/core 0 or 64 2.0

See also

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References

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  1. ^ "Inventing Itanium: How HP Labs helped create the next-generation chip architecture". HP Labs. 2001-06-01. Archived from the original on 2002-02-07. Retrieved 2024-03-24.
  2. ^ "One Year Ago". (26 February 1987). Computer Business Review.
  3. ^ Rosenbladt, Peter (September 1987). "In this Issue" (PDF). Hewlett-Packard Journal. 38 (9): 3. Archived (PDF) from the original on 2019-04-26. Retrieved 2018-06-08. ... In the March 1987 issue we described the HP 3000 Series 930 and HP 9000 Model 840 Computers, which were HP's first realizations of HP Precision Architecture in off-the-shelf TTL technology. ...
  4. ^ "How long will HP continue to support HP 9000 systems?". Archived from the original on 2012-02-19. Retrieved 2008-02-29.
  5. ^ "HP Completes Its PA-RISC Road Map With Final Processor Upgrade". Archived from the original on 2008-02-13. Retrieved 2007-07-24.
  6. ^ Worley, William S. (August 1986). "Hewlett-Packard Precision Architecture: The Processor" (PDF). Hewlett-Packard Journal. 37 (8): 4–22. The HP Precision Architecture development program, known within HP as the Spectrum program, ...
  7. ^ Fotland, David A.; Shelton, John F.; Bryg, William R.; La Fetra, Ross V.; Boschma, Simin I.; Yeh, Allan S.; Jacobs, Edward M. (March 1987). "Hardware Design of the First HP Precision Architecture Computers". Hewlett-Packard Journal. 38 (3): 4–17. Retrieved 6 October 2020.
  8. ^ "Hewlett-Packard Precision Architecture: The Processor" (PDF). p. 10. Retrieved 2023-12-02.
  9. ^ DeRosa, John A.; Levy, Henry M. (1987). "An Evaluation of Branch Architectures". Proceedings of the 14th annual international symposium on Computer architecture. pp. 10–16. doi:10.1145/30350.30352. ISBN 0-8186-0776-9. Retrieved 2024-01-27.
  10. ^ "Hewlett-Packard Precision Architecture: The Processor" (PDF). p. 6. Retrieved 2023-12-07.
  11. ^ Smotherman, Mark (2 July 2009). Recent Processor Architects Archived 2012-09-10 at the Wayback Machine.
  12. ^ Paul Weissmann. "Early PA-RISC Systems" Archived 2014-10-02 at the Wayback Machine.
  13. ^ Walpole, Jonathan; Hakanson, Marion; Inouye, Jon; Konuru, Ravi (January 1992). Porting Chorus to the PA-RISC: Project Overview (PDF) (Report). Oregon Graduate Institute Of Science And Technology. Archived from the original on 12 June 2023.
  14. ^ a b c "PA-RISC Processors"
  15. ^ Marston, A.; et al. (1987). "A 32b CMOS single-chip RISC type processor". 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. pp. 28–29. doi:10.1109/ISSCC.1987.1157145. S2CID 61007482.
  16. ^ Yetter, J.; et al. (1987). "A 15 MIPS 32b Microprocessor". ISSCC 1987. pp. 26–27. doi:10.1109/ISSCC.1987.1157220. S2CID 58782915.
  17. ^ Boschma, Brian D.; et al. (1989). "A 30 MIPS VLSI CPU". IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers. pp. 82–83, 299. doi:10.1109/ISSCC.1989.48191. S2CID 53932361.
  18. ^ a b "HP L1000 & L2000 (rp5400/rp5450) Servers" Archived 2018-01-02 at the Wayback Machine, openpa.net
  19. ^ "Third-Party PA-RISC Processors from Hitachi, Winbond, OKI – OpenPA.net".
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