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Minimal instruction set computer

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Minimal instruction set computer (MISC) is a central processing unit (CPU) architecture, usually in the form of a microprocessor, with a very small number of basic operations and corresponding opcodes, together forming an instruction set. Such sets are commonly stack-based rather than register-based to reduce the size of operand specifiers.

Such a stack machine architecture is inherently simpler since all instructions operate on the top-most stack entries.

One result of the stack architecture is an overall smaller instruction set, allowing a smaller and faster instruction decode unit with overall faster operation of individual instructions.

Characteristics and design philosophy[edit]

Separate from the stack definition of a MISC architecture, is the MISC architecture being defined by the number of instructions supported.

  • Typically a minimal instruction set computer is viewed as having 32 or fewer instructions,[1][2][3] where NOP, RESET, and CPUID type instructions are usually not counted by consensus due to their fundamental nature.
  • 32 instructions is viewed as the highest allowable number of instructions for a MISC, though 16 or 8 instructions are closer to what is meant by "Minimal Instructions".
  • A MISC CPU cannot have zero instructions as that is a zero instruction set computer.
  • A MISC CPU cannot have one instruction as that is a one instruction set computer.[4]
  • The implemented CPU instructions should by default not support a wide set of inputs, so this typically means an 8-bit or 16-bit CPU.
  • If a CPU has an NX bit, it is more likely to be viewed as being a complex instruction set computer (CISC) or reduced instruction set computer (RISC).
  • MISC chips typically lack hardware memory protection of any kind, unless there is an application specific reason to have the feature.
  • If a CPU has a microcode subsystem, that excludes it from being a MISC.
  • The only addressing mode considered acceptable[by whom? – Discuss] for a MISC CPU to have is load/store, the same as for reduced instruction set computer (RISC) CPUs.
  • MISC CPUs can typically have between 64 KB to 4 GB of accessible addressable memory—but most MISC designs are under 1 megabyte.

Also, the instruction pipelines of MISC as a rule tend to be very simple. Instruction pipelines, branch prediction, out-of-order execution, register renaming, and speculative execution broadly exclude a CPU from being classified as a MISC architecture.

While 1-bit CPUs are otherwise obsolete (and were not MISCs nor OISCs), the first carbon nanotube computer is a 1-bit one-instruction set computer, and has only 178 transistors, and thus likely the lowest-complexity (or next-lowest) CPU produced so far (by transistor count).

History[edit]

Some of the first digital computers implemented with instruction sets were by modern definition minimal instruction set computers.

Among these various computers, only ILLIAC and ORDVAC had compatible instruction sets.

Early stored-program computers[edit]

  • The IBM SSEC had the ability to treat instructions as data, and was publicly demonstrated on January 27, 1948. This ability was claimed in a US patent issued April 28, 1953.[6] However, it was partly electromechanical, not fully electronic. In practice, instructions were read from paper tape due to its limited memory.[7]
  • The Manchester Baby, by the Victoria University of Manchester, was the first fully electronic computer to run a stored program. It ran a factoring program for 52 minutes on June 21, 1948, after running a simple division program and a program to show that two numbers were relatively prime.
  • The Electronic Numerical Integrator and Computer (ENIAC) was modified to run as a primitive read-only stored-program computer (using the Function Tables for program read-only memory (ROM) and was demonstrated as such on September 16, 1948, running a program by Adele Goldstine for von Neumann.
  • The Binary Automatic Computer (BINAC) ran some test programs in February, March, and April 1949, although was not completed until September 1949.
  • The Manchester Mark 1 developed from the Baby project. An intermediate version of the Mark 1 was available to run programs in April 1949, but was not completed until October 1949.
  • The Electronic Delay Storage Automatic Calculator (EDSAC) ran its first program on May 6, 1949.
  • The Electronic Discrete Variable Automatic Computer (EDVAC) was delivered in August 1949, but it had problems that kept it from being put into regular operation until 1951.
  • The Commonwealth Scientific and Industrial Research Automatic Computer (CSIRAC, formerly CSIR Mk I) ran its first program in November 1949.
  • The Standards Eastern Automatic Computer (SEAC) was demonstrated in April 1950.
  • The Pilot ACE ran its first program on May 10, 1950 and was demonstrated in December 1950.
  • The Standards Western Automatic Computer (SWAC) was completed in July 1950.
  • The Whirlwind was completed in December 1950 and was in actual use in April 1951.
  • The first ERA Atlas (later the commercial ERA 1101/UNIVAC 1101) was installed in December 1950.

Design weaknesses[edit]

The disadvantage of a MISC is that instructions tend to have more sequential dependencies, reducing overall instruction-level parallelism.

MISC architectures have much in common with some features of some programming languages such as Forth's use of the stack, and the Java virtual machine. Both are weak in providing full instruction-level parallelism. However, one could employ macro-op fusion as a means of executing common instruction phrases as individual steps (e.g., ADD,FETCH to perform a single indexed memory read).

Notable CPUs[edit]

Probably the most commercially successful MISC was the original INMOS transputer architecture that had no floating-point unit. However, many 8-bit microcontrollers, for embedded computer applications, qualify as MISC.

Each STEREO spacecraft includes two P24 MISC CPUs and two CPU24 MISC CPUs.[8][9][10][11]

See also[edit]

References[edit]

  1. ^ Ting, Chen-hanson; Moore, Charles H. (1995). "MuP21: A High Performance MISC Processor". UltraTechnology. Offete Enterprises.
  2. ^ US patent 5481743A, Baxter, Michael A., "Minimal instruction set computer architecture and multiple instruction issue method", published 1996-01-02, issued 1996-01-02, assigned to Apple 
  3. ^ Halverson, Richard Jr.; Lew, Art (1995). An FPGA-Based Minimal Instruction Set Computer (Technical report). Information and Computer Sciences Department, University of Hawai. p. 23. ICS-TR-94-28.
  4. ^ Kong, J.H.; Ang, L.-M.; Seng, K.P. (2010). "Minimal Instruction Set AES Processor using Harvard Architecture". 2010 3rd International Conference on Computer Science and Information Technology. pp. 65–69. doi:10.1109/ICCSIT.2010.5564522. ISBN 978-1-4244-5540-9.
  5. ^ Robertson, James E. (1955). Illiac Design Techniques: report number UIUCDCS-R-1955-146 (Report). Urbana–Champaign, Illinois: Digital Computer Laboratory, University of Illinois at Urbana–Champaign.
  6. ^ US patent 2636672, Hamilton, Francis E.; Hughes, Ernest S. Jr. & Rowley, Russell A. et al., "Selective Sequence Electronic Calculator", issued 1953-04-28, assigned to IBM 
  7. ^ Grosch, Herbert R.J. (1991). Computer: Bit Slices From a Life. Third Millenium Books. ISBN 978-0-8873-3085-8.
  8. ^ Mewaldt, R. A.; Cohen, C. M. S.; Cook, W. R.; Cummings, A. C.; et al. "3.5.2 The Minimal Instruction Set Computer (MISC)". The Low-Energy Telescope (LET) and SEP Central Electronics for the STEREO Mission (PDF) (Report). p. 20.
  9. ^ Russell, C.T., ed. (2008). The STEREO Mission. Springer. ISBN 978-0-387-09649-0.
  10. ^ Ting, C-H; Cook, W.R. (2001). P24 MISC Microprocessor User's Manual (Technical report). eMAST Technology. STEREO-CIT-005.A.
  11. ^ CPU24 Microprocessor User's Manual (Technical report). NASA. October 2003. Version 5 Actel for Stereo HET.

External links[edit]

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